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ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)

  • Pune, India
  • Pay not stated
  • Detected 7 days ago

Key facts

Location
Pune, India
Workplace
Not stated
Pay
Not stated
Contract
Full-time
Detected
3 Nov 2026
Posted
Not stated

About the role

The employer’s listing didn’t include a summary.

The full description is on Cisco’s careers site (opens in a new tab).